1. Field of the Invention
This invention relates to digital systems. In particular, this invention relates to signal synchronization in a digital computer system.
2. Description of the Related Art
With the increase of system clock frequencies in digital computer systems, the difficulty of maintaining data signal synchronization in these digital computer systems, for example by distributing a global clock signal to the subsystems of these digital computer systems, increases correspondingly.
FIG. 1A is a block diagram illustrating a method of synchronizing data signals by distributing a global clock signal to a plurality of subsystems, e.g., a source subsystem 120 and a destination subsystem 130, located at different physical locations of a digital computer system 100. Computer system 100 also includes a system clock generator 110 and a corresponding plurality of delays, e.g., a source delay 112 and a destination delay 113. System clock generator 110 is coupled to a source clock generator 125 and a destination clock generator 135 of subsystems 120, 130 via delays 112, 113, respectively.
Referring now to the timing diagram of FIG. 1B, in order to synchronize source clock generator 125 and destination clock generator 135, suitable time delays are selected for delays 112 and 113 such that the total time a clock pulse takes to propagate from the output node of system clock generator 110 to either input nodes of source clock generator 125 or destination clock generator 135 are the same or close to the same. In other words, the difference in propagation through delays 112, 113 compensate for the relative propagation delays in the source and destination clock lines. Typically, a skew of up to 5% can be tolerated.
In this example, a source clock (SRC.sub.-- CLK) signal at the input node of source clock generator 125, which is the global clock (SYS.sub.-- CLK) signal delayed by the source line, i.e., the source line clock (SRC.sub.-- LINE.sub.-- CLK) signal, further delayed by source delay 112, is synchronized with or almost synchronized with a destination clock (DEST.sub.-- CLK) signal at the input node of destination clock generator 135, i.e., the destination line clock (DEST.sub.-- LINE.sub.-- CLK) signal, further delayed by destination delay 113. As a result, data signals can be exchanged between subsystems 120 and 130 without any additional timing signals since both source clock generator 125 and destination clock generator 135 are kept synchronized by the SRC.sub.-- CLK and DEST.sub.-- CLK signals.
As shown in FIG. 1B, system 100 is capable of transferring a unit of data from source subsystem 120 to destination subsystem 130 per cycle of the SYS.sub.-- CLK signal. Data transmitted before the rising edge of the SYS.sub.-- CLK signal by source subsystem 120 is received before the next rising edge of the SYS.sub.-- CLK signal by destination subsystem 130. Accordingly, there is no need to resynchronize data at destination subsystem 130. The maximum rate of data transfer is determined by the skew between the SRC.sub.-- CLK and DEST.sub.-- CLK signals, and by the propagation delay of data transfers from source subsystem 120 to destination subsystem 130.
FIG. 2 is a block diagram illustrating another method of synchronizing data signals, where instead of distributing a global clock signal to subsystems, a source subsystem 220 is required to provide a source-synchronous clock (SRC.sub.-- SYN.sub.-- CLK) signal whenever data is transferred between source subsystem 220 and a destination subsystem 230. In exemplary system 200, source subsystem 220 and destination subsystem 230 include source clock generator 225 and destination clock generator 235, respectively. Destination subsystem 230 also includes latches 232,233, and 234 coupled in series.
The propagation delay of data and the SRC.sub.-- SYN.sub.-- CLK signal are closely matched. The maximum data transfer rate is not limited by the total propagation delay, but by the skew between data and the SRC.sub.-- SYN.sub.-- CLK signal. This technique allows data transfer rates that are higher than SRC.sub.-- CLK signal of system 100.
Although the DEST.sub.-- CLK signal of destination subsystem 130 has the same frequency as the SRC.sub.-- SYN.sub.-- CLK signal, the skew of DEST.sub.-- CLK signal with respect to SRC.sub.-- SYN.sub.-- CLK signal is unknown and cannot be predicted with any accuracy. As a result, clocking the input data node of latch 233 of destination subsystem 130 with the DEST.sub.-- CLK signal can result in metastability conditions in latch 233. To avoid the metastability problem, the output signal of latch 233 is relatched into latch 234, so that any metastability condition at the register 233 will have been resolved by the time the data is clocked by latch 234.
This two stage clocking introduces a penalty of one latent clock cycle. In some technologies, the metastability problem may not be resolvable by one latent clock cycle, and additional latent clock cycles may be necessary.
Hence, there is a need for a simple and effective scheme for reducing the lag time to one or less system clock cycle and which is capable of transferring more than one unit of data per system clock cycle.